- Beneficios de acuerdo a la LFT
- Seguro de vida
- Fondo de ahorro
- Seguro de gastos médicos
ASIC DFT Engineer
North American Production Sharing de México, S.A. de C.V.
Tijuana, Baja California
Abril 28 2025
Compartir:
Corporativo
Giro
Maquiladora (Export.)
Actividad principal
Administración de maquiladoras.
Número de empleados
10000
Sitio Web corporativo
Descripción y detalle de las actividades
Join our CAD team and shape the future of Design-for-Testability (DFT) in the semiconductor industry!
We’re looking for an innovative DFT CAD Engineer to support the deployment of advanced flows enabling cutting-edge process nodes. This role provides a unique opportunity to collaborate across design, production testing, and yield analysis teams, driving the development of state-of-the-art solutions that fuel the company's success.
Responsibilities
- Will be part of DFTCAD automation team, developing methodology and flows to support end-2-end DFT/DFX solution, and provide support and training
- Collaborate with SoC design, product and test engineer teams to drive standardization of DFT/ATPG methodology and flow across the company.
- Work closely with multiple EDA tool vendors to resolve day-2-day issues, help to drive vendor solution
- Collect and evaluate requirements with consideration of improving design flow efficiency, test quality and lower test cost to improve DFT flow and methodology
Experiencia y requisitos
Qualifications
- 3+ years of experience in DFT/DFD/DFX, MS or PhD degree in EE or related field, or equivalent experience
- Core DFT skills for this position include: scan insertion, Memory BIST implementation, JTAG/IJTAG, at-speed test, ATPG, fault simulation, silicon diagnostic, scan compression, IDL/PDL, SSN, SEQ, Core-based test methodology and IO wrapping, pattern retargeting
- Experience developing automation for DFT flow and architecting the DFT methodology
- Strong coding experience with hands on experience using TCL, Python/Perl, Scripting, and strong analytical debug and problem-solving skills
- Good exposure with industrial DFT tools including Siemens, Synopsys or equivalent
- Deep understanding of SoC design, low power, timing exceptions and complex clock structures
- Strong analytical and debugging experience for ATPG DRC, product manufacturing pattern failures and Design for Debug concept and implementation
- Excellent team spirit, strong ownership and openness, highly motivated
Beneficios
Número de vacantes 1
Área Electrónica
Contrato Permanente
Modalidad Presencial
Turno Diurno
Jornada Tiempo Completo
Horario
- Tiempo completo
- Turno Matutino
- Lunes a viernes
Estudios Carrera con título profesional
Inglés Hablado: Avanzado, Escrito: Avanzado
Disponibilidad p. viajar No